News

COM-HPC Mini pinout and footprint defined

WAKEFIELD, MA., USA. PICMG, a leading consortium for the development of open embedded computing specifications, announces that the COM-HPC committee has finalized the pinout and dimension definitions for the COM-HPC Mini form factor in record time. This means that the vast majority of the details of the COM-HPC Mini standard have been defined and documentation has already begun. Reaching this critical milestone enables PICMG members to start design work on compliant modules so that embedded OEMs and developers will have access to an elaborated ecosystem shortly after specification launch. The outstanding performance of the 15 member companies in the COM-HPC Mini working group reflects the high market relevance and demand for a high-performance credit-card-sized Computer-on-Modules standard. Only 12 weeks passed between the approved Statement of Work and the final definition of the mechanics and pinout by the working group.
“The definition of COM-HPC Mini is happening almost at the speed of light. If the working group maintains this performance, and I see no reason to slow it down as there are no significant technical challenges left to address, I am confident to have a release candidate available for the PICMG release process in Q1 2023, and a published specification by Q2 2023. I anticipate first product announcements will be closely tied to the publication date,” explains Christian Eder, Chairman of the COM-HPC technical committee and Director Product Marketing at congatec.
“The ‘HPC’ in COM-HPC stands for ‘High-Performance Computing’ but we now use it to refer to the ‘High-Performance Crew’ developing the COM-HPC family of specifications. The team’s performance is keeping pace with the rapidly changing embedded applications and technologies,” adds Jessica Isquith, PICMG President.
Details on COM-HPC Mini
The COM-HPC Mini pinout specification defines the use of one connector instead of the two implemented for the larger COM-HPC Client and Server modules (Sizes A -E), just like COM Express Mini compared to COM Express Type 6. But with COM-HPC, half the number of signal pins still means 400 signal lanes, which equals 90% of the capacity that COM Express Type 6 modules provide. COM-HPC Mini offers a 50% smaller footprint compared to COM-HPC Client Size A modules, the currently smallest available COM-HPC form factor. Such extremely small modules measuring only 60 x 95 mm are required for high-end embedded computer logic in devices such as top-hat rail PCs for control cabinets in building and industrial automation, or portable test and measurement devices. In addition, the new specification will enable engineers to integrate state-of-the-art computer interface technologies such as PCIe Gen4 and Gen5 into ultra-small processing units that provide highest performance. As the new specification will come with a focused high-performance pinout and will comply with the entire COM-HPC ecosystem, it is expected to become the high-end standard on top of the PICMG’s earlier COM Express Mini standard. PICMG expects the COM Express specification to continue leading the COM market for many years as it meets numerous standard application requirements now to be allocated in the mid-range performance sector.

The working group comprises 15 member companies and is sponsored by ADLINK, Kontron and congatec. Christian Eder of congatec is the Chairman and Stefan Milner is the specification Editor.

For more information on COM-HPC, visit www.picmg.org/openstandards/com-hpc or purchase the specification for $750 from www.picmg.org/product/com-hpc-module-base-specification-revision-1-15.
More on PICMG’s range of open, modular computing standards can be found at www.picmg.org.

About PICMG
Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are over 130 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.
Key standards families developed by PICMG include COM-HPC, COM Express, ModBlox7, IoT.1, CompactPCI, AdvancedTCA, MicroTCA, AdvancedMC, CompactPCI Serial, COM Express, SHB Express, MicroSAM, and HPM (Hardware Platform Management). For more information visit www.picmg.org.

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PICMG COM-HPC 1.15 and COM.0 R3.1 continue evolution to support high-performance, mixed-criticality, and cost-optimized IoT edge, gateway, and server designs with strict time-to-market requirements.

WAKEFIELD, MA. PICMG, a leading consortium for the development of open embedded computing specifications, has announced major updates to the COM-HPC and COM Express families of computer-on-module (COM) standards with the ratification of Functional Safety (FuSa) extensions to COM-HPC (COM-HPC 1.15) and COM Express Revision 3.1 (COM.0 R3.1), which adds 16 Gbps connectors, support for PCI Express Gen 4, USB 4, SATA Gen 3 optimizations, and other enhancements.

COM-HPC 1.15 is a set of safety extensions that expand the FuSa capabilities of “safety island” blocks available on modern chipsets out to the broader system. Available on all COM-HPC form factors – including the upcoming COM-HPC Client Mini – COM-HPC FuSa extensions define a dedicated SPI signal that connects health and status monitoring features of such blocks to a FuSa “Safety Controller” located on COM-HPC carrier cards where any findings can be processed for external use.

The COM-HPC 1.15 architecture thus enables the creation of mixed-criticality multicore embedded systems by providing a direct path to redundancy and fail-safe process implementation for developers of industrial machine control, train and wayside control, robotics, autonomous vehicles, avionics, and other critical systems.

“With the small size definition of the upcoming Mini specification and the recent FuSa extensions, COM-HPC covers all use cases I can think of,” says Christian Eder, Chair of the COM-HPC technical committee and Director Product Marketing at congatec. “COM-HPC is the most complete computer module definition ever. I expect an extremely fast growth for scalable and compute-power hungry embedded applications based on COM-HPC technology.”

The COM-HPC 1.15 specification effort is sponsored by ADLINK, congatec, and Kontron.

COM Express Revision 3.1 continues the evolution of the electronics industry’s most popular COM standard by adding support for PCIe Gen 4 and an updated 16 Gbps connector across the family’s Type 6, 7, and 10 pinouts. SATA Gen 3 signal integrity and loss budget information has also been added for each Type.

These improvements join pinout-specific upgrades including optional USB4 (Type 6), MIPI-CSI connectors (Types 6, 10), SoundWire (Types 6, 10), as well as an additional general-purpose SPI interface (Types 6, 10). A CEI signaling-enabled 10 GbE interface and IPMB management interface are also now defined in the Type 7 pinout as part of COM.0 R3.1.

COM Express Revision 3.1 Type 6 and Type 10 hardware is fully backward-compatible with 3.0 modules and carrier boards, while Revision 3.1 Type 7 modules are backward compatible apart from 10GBASE-KR Ethernet side-band signals and a second PCIe reference clock not included on R3.0 modules.

“The PICMG COM Express specification just had its 23^rd anniversary. During this time, the specification has been updated to support the latest interfaces while focusing on maintaining backwards compatibility. Revision 3.1 is no exception,” says Jeff Munch, CTO of ADLINK Technology and Chairman of the COM Express subcommittee. “In the latest release of the COM Express specification the subcommittee has added support for PCI Express Gen 4, USB4, and newer 10G side-band interfaces while maximizing backwards compatibility.

“These new interfaces will allow COM Express to continue to fill its role as a leading computer-on-module standard.”

For more information on the COM-HPC FuSa extensions specification, visit www.picmg.org/openstandards/com-hpc or purchase the specification for $750 from www.picmg.org/product/com-hpc-module-base-specification-revision-1-15.

For more on the COM Express family of specifications, go to www.picmg.org/openstandards/com-express or purchase the latest specification revision from www.picmg.org/product/com-express-module-base-specification-rev-3-1.

More on PICMG’s range of open, modular computing standards can be found at www.picmg.org.

About PICMG
Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are over 130 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.

Key standards families developed by PICMG include COM Express, COM-HPC, ModBlox7, IoT.1, CompactPCI, AdvancedTCA, MicroTCA, AdvancedMC, CompactPCI Serial, COM Express, SHB Express, MicroSAM, and HPM (Hardware Platform Management). For more information visit www.picmg.org.

Wakefield, MA., USA / Nuremberg, Germany, June 23, 2022 – PICMG, a leading consortium for the development of open embedded computing specifications, announces that the MicroTCA Working Group is working on the next generation of the MTCA architecture specifications initially launched in 2006. Efforts target improvements for time sensitive and high bandwidth applications such as in high-energy physics. Current work includes accommodations for the next generation of CPUs and FPGAs that will natively support PCIe gen 5. Future applications in industry require this higher bandwidth i.e. for image processing, signal detection, data acquisition. As current CPU speeds are limited by 80 W per slot power limit the support of more power for faster CPUs is on the task list as well. Future applications will also require other kinds of high- and low-speed fabrics paired with more flexibility in system design. The science market segment for high frame rate Megapixel detectors of the actual photon experiments requires even higher throughput. Thus, all these demands are scheduled to become part of the new releases of these successful specifications. With all these improvements MicroTCA continues to be an pro-active specification with significant updates to support high-bandwidth backplane interconnects. Latest update of the specs happened as recently as 2020.

“I am more than happy that the MicroTCA Working Group is so pro-actively addressing the recent demands. The new spec will find its way into many different vertical markets due to the flexibility of MicroTCA!”, says Heiko Koerte, VP and Director Sales & Marketing of N.A.T., “Applications in industrial automation, medical, telecommunication and networking, aerospace and transportation will not only benefit form these new features but also from how easily MicroTCA can be adapted to the exact needs. More than 16.500 MCHs just from N.A.T and many more I/O and compute cards delivered to the field speak for themselves. The wide spread of MicroTCA definitely makes it both a technically and commercially attractive solution!”.

About MicroTCA

MicroTCA® is a modular, open standard for building high-performance, backplane-based switched fabric computer systems in a small form factor.

MicroTCA has become the de facto standard for precision timing and synchronization equipment at world-renowned particle accelerators CERN, DESY, ESS, XFEL, KEK, SLAC, and others. Its architecture and features are also consistent with the Modular Open Systems Approach (MOSA) being adopted as part of the U.S. Department of Defense (DoD) electronic media acquisition policy.

Originally designed for edge telecom and networking use cases, the core MTCA.0 base specification defines the mechanical and electrical characteristics of a MicroTCA backplane, card cage, power subsystem, cooling, and system management. Since being ratified in 2011, the MTCA Base specification has been revised to support 10GBASE-KR and 40GBASE-KR4 Ethernet fabrics and spawned four additional sub-specifications adapted for data acquisition, control, and telemetry in markets such as high-energy physics, avionics, defense, mobile infrastructure, and others.

• MicroTCA.0 – The Base specification defines MicroTCA’s electrical, mechanical, thermal, and management characteristics, including support for implemented in MicroTCA.0 Revision 2.0 in 2020.

• MicroTCA.1 – Adds ruggedization features and forced-air cooling.

• MicroTCA.2 – Expands shock, vibration, and temperature operation, allowing for both air and conduction cooling.

• MicroTCA.3 – Continues to increase compliance threshold for shock, vibration, and temperature and requires the use of conduction cooling.

• MicroTCA.4 – Adds features for the scientific community such as Rear Transition Modules (RTMs), which improve RF filtering, pre- and post-processing, clock generation, etc.

Developed as a reduced-footprint alternative to the popular AdvancedTCA family of specifications, MicroTCA defines a backplane-based system for plug-in Advanced Mezzanine Cards (AdvancedMCs). AdvancedMCs are available in different sizes (Full-size, Mid-size, Compact) and can be sourced from multiple vendors to add compute, storage, I/O, and other functionality to a MicroTCA chassis without modification. As mentioned previously, the MTCA.4 sub-specification also adds support for RTMs that increase system expansion possibilities in scientific applications.

A single MicroTCA system contains up to 12 AdvancedMCs slots, and up to two MicroTCA Carrier Hubs (MCHs). MCHs provide intelligent platform management, power delivery, and facilitate switching over Ethernet, PCIe, and/or Serial RapidIO backplane interconnect fabrics.

To learn more about the PICMG MicroTCA family of specifications, download the Short Form Specification for free at https://www.picmg.org/wp-content/uploads/MicroTCA_Short_Form_Sept_2006.pdf. You can also purchase Revision 2.0 of the MicroTCA Base Specification for $750 from https://www.picmg.org/product/microtca-base-specification-r2-0.

The current committee is led by Kay Rehlich of DESY, Heiko Koerte of N.A.T. and Thomas Holzapfel from powerBridge.

About PICMG
Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are over 130 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.

Key standards families developed by PICMG include COM Express, COM-HPC, ModBlox7, IoT.1, CompactPCI, AdvancedTCA, MicroTCA, AdvancedMC, CompactPCI Serial, COM Express, SHB Express, MicroSAM, and HPM (Hardware Platform Management). https://www.picmg.org