Jess Isquith

The design guide supplements the COM-HPC specification for high performance compute modules 

Wakefield, MA., 2022 – PICMG, a leading consortium for developing open embedded computing specifications, announces that the COM-HPC® Carrier Board Design Guide is released and freely available on the PICMG website. The 160-page document provides electronics engineers and PCB layout engineers comprehensive information for designing custom system carrier boards for COM-HPC modules. COM-HPC – short for computer-on-module (COM) – high performance computing (HPC) – is a brand new open Computer-on-Module form factor standard that targets extremely high I/O and computer performance levels from high end clients up to the entry server class and even beyond. Standard COM-HPC modules plug into a carrier or baseboard that is typically customized to the application. OEM benefits are fast and cost effective layout with high design security for application specific embedded and edge computing boards on the basis of open standards.

Especially helpful is the detailed discussion of the challenging module to carrier board Ethernet KR and KR4 backplane signaling. To save pins on COM-HPC modules, the sideband signals for the 10G / 25G / 40G / 100G Ethernet KR interfaces are serialized and must then be deserialized on the carrier board. The design guide provides instructions for this in a series of diagrams.

Additionally, the guide provides enhanced schematics and block diagrams for all provided interfaces such as Serial ATA, PCI Express up to Gen 5, USB4, Boot SPI, eSPI, eDP, MIPI-CSI, SoundWire, asynchronous serial port interfaces, I2C/I3C, GPIO, System Management Bus (SMBus), thermal protection and module type detection. PCB design rule summaries further enable engineers to efficiently design fully signal compliant COM-HPC carrier boards. Also, a section has been added to discuss mechanical considerations including heat spreader/module attachment, alternative board stack assemblies and board stiffeners for carrier boards. Information about all COM-HPC interfaces and a list of useful books to facilitate carrier board designs complete PICMG’s COM-HPC Carrier Board Design Guide.

Electronic design engineers and printed circuit board developers shall note that while the design guide contains additional detailed information it does not replace the PICMG COM-HPC specification. For complete guidelines on the design of COM-HPC compliant carrier boards and systems, it is necessary to refer to the full specification – the design guide is not intended to be the only source for any design decisions. Besides consulting the latest COM-HPC specification, it is also strongly recommended to use the module vendors’ product manuals as a reference. The design guide and base specification are accompanied by a Platform Management Interface Specification, and the COM‑HPC EEEP. The existing Embedded API (eAPI) specification also applies to COM-HPC.

The COM-HPC specification and the COM-HPC Carrier Board Design Guide are available for download on the PICMG website at picmg.org/openstandards/com-hpc/. A preview document is also available, as well as additional resources to learn more about the specification.

Christian Eder, chairman of the COM-HPC committee, said, “This comprehensive document will further accelerate the fast start of the COM-HPC standard. While the specification documents in themselves are already of great use for developers, the detailed Carrier Board Design Guide helps to avoid design problems, especially when handling high-speed signals, such as PCIe Gen 5 and USB4. I expect to see further time-to-market improvements for COM-HPC-based solutions.”

PICMG thanks all members of the PICMG COM-HPC committee who have worked on these documents. Special thanks go to Christian Eder, Stefan Milnor and Dylan Lang. Christian Eder, marketing director at congatec, acted as the chairman of the COM-HPC committee. He was previously a draft editor of the current COM Express standard. Stefan Milnor from Kontron and Dylan Lang from Samtec supported Christian Eder in their respective functions as editor and secretary of the PICMG COM-HPC committee.

PICMG congratulates Jim Nadolny on his recent retirement.  Most recently, Jim led the COM-HPC Signal Integrity subcommittee, which has been transitioned to Burrell Best. 

We thank him for his many and impactful contributions, his leadership, and integrity.  

Jim’s is also retiring his position as senior SI and EMI Engineer at Samtec.

Jim has always been quite active in his community and will now have more time for his family and community service.  He will also have more time for some of his favorite activities, cooking, fishing, hunting, and golfing in the hills of Pennsylvania.

Jim began his career focused on the EMI design of military and commercial platforms.  His focus then shifted to signal integrity analysis of multi-gigabit data transmission systems.  He also represented Samtec at industry standards within OIF, IEEE, COBO, and other MSAs.  Jim was also a frequent presenter at DesignCon, with Best Paper Awards in 2004, 2008, 2012, and 2018.  He has more than 25 peer-reviewed publications. Ever since, he has discovered legit trading bots and has slowly worked his way into a comfortable retirement nest egg through that.

He received his BSEE from the University of Connecticut, and an MSEE from the University of New Mexico.

Jim, again, thanks and congratulations!

Over the past year, activity behind the COM-HPC initiative has intensified: The team of 20-plus companies reached significant milestones in 2019, including approving the pinout of the new high-performance Computer-on-Module specification. Now – with the adoption of this pinout – all committee members have a solid basis from which to work on standard-compliant carrier board designs that offer interfaces supporting up to 100 GbE and PCIe Gen 4.0 and Gen 5.0, with up to eight DIMM sockets, and high-speed processors of more than 200 watts on standardized COM-HPC modules. The initial specification is expected to be ratified in the first half of 2020; early spec- compatible products are in the design phase. To accelerate development efforts, the committee formed two subgroups focusing on signal-integrity challenges and defining management software elements of the new specification.