What’s New

February 29, 2024

Members Only Series: Jens Hagemayer of Bielefeld University and the COM-HPC plus CXL Opportunity

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The Members Only interview series highlights leaders from within PICMG and throughout the open standards development community. We recognize their contributions and seek insight into their thought processes and strategies driving open technology-powered industries forward.

This issue we introduce Jens Hagemayer, a research associate at the Bielefeld University. Jens and his team have been intimately involved in the development of COM-HPC since its inception, championing the use of heterogeneous modules designed around FPGAs. Now they are investigating ways that Compute Express Link (CXL) specifications can take COM-HPC into new use cases.

PICMG: Can you describe your work outside of PICMG as well as the role you played in development of the COM-HPC specification? 

JENS: I am currently engaged in research at Bielefeld University, focusing on the development of heterogeneous and reconfigurable computing technologies for a wide range of applications. These include the Internet of Things (IoT), edge computing, cloud computing, and high-performance computing (HPC).

My involvement with the early stages of the COM-HPC specification centered on leading the development of the Platform Management Interface Specification and expanding the Embedded EEPROM Specification for COM-HPC. 

PICMG: You recently raised awareness about the CXL standard within the COM-HPC community. What is CXL and why is it relevant for PICMG COM-HPC developers and users?

JENS: CXL, or Compute Express Link, is a high-speed, high-capacity interconnect standard that facilitates efficient communication between CPUs, memory, and peripherals using the PCIe physical layer. Its support for cache coherency, disaggregation, and scalable architectures makes it a compelling choice for modular form factors like COM-HPC, driving its popularity among developers and users seeking advanced computing solutions.

PICMG: Why is CXL 3.1 significant in the context of COM-HPC? What use cases or capabilities will it drive in the COM-HPC ecosystem?

JENS: CXL introduces features that cater to the demanding requirements of cloud and high-performance computing systems. Its emphasis on scalable architectures, disaggregation, and cache coherency is particularly relevant for COM-HPC, offering the potential to revolutionize the way modular computing platforms are designed and utilized. 

The integration of CXL into COM-HPC could facilitate the development of more sophisticated computing solutions, enabling the seamless coupling of specialized accelerators and the establishment of cache-coherent multi-socket systems. These advancements promise to unlock new possibilities for COM-HPC applications, ranging from data-intensive analytics to AI and machine learning workloads, driving innovation in modular computing technologies.

PICMG: Given that CXL targets PCIe, has it been compatible with COM-HPC to date?

JENS: The relationship between CXL and COM-HPC is fundamentally influenced by CXL’s reliance on the PCIe physical layer for connectivity. This means that while direct compatibility between previous versions of CXL and COM-HPC has not been explicitly defined, the architectural underpinnings allow for potential integration. 

The absence of CXL in the current COM-HPC specification, coupled with the lack of support in existing modules, suggests that the integration of CXL represents a forward-looking opportunity for enhancing COM-HPC. Such integration is anticipated to require minimal modifications to the specification, paving the way for future advancements in modular computing.

PICMG: What does the COM-HPC community need to know about the CXL market or technical requirements to capitalize on the opportunity?

JENS: To fully leverage the potential that CXL brings to the COM-HPC community, it is crucial to understand the intricacies of CXL’s market dynamics and technical specifications. This involves a deep dive into the architecture of CXL, including its device types—such as Type 1 for I/O devices, Type 2 for cache-coherent devices, and Type 3 for memory expander devices. Additionally, understanding the topology options that CXL supports, including switch-based topologies for larger, more complex systems, can empower developers to design COM-HPC solutions that are both innovative and future-proof. 

Staying abreast of the evolving CXL specifications and market trends will enable the COM-HPC community to identify new opportunities for integration and application, ensuring that COM-HPC modules remain at the forefront of technological advancement.

PICMG: What are you and Bielefeld University doing with respect to CXL today?

JENS: We are working on integrating CXL within the RISC-V ecosystem, a venture that holds promising implications for the future of computing architectures. Our work focuses on the development of innovative bridge technologies that facilitate communication between the RISC-V Coherent Hub Interface (CHI) and CXL, using FPGA-based modules, which we refer to as microservers. 

This endeavor is not just about bridging two technical standards; it’s about creating a foundation for next-generation computing platforms that can seamlessly integrate diverse processing and memory resources. By developing these bridges, we aim to enable more efficient, scalable, and flexible computing architectures that can cater to the demanding requirements of modern applications, ranging from AI and machine learning to big data analytics.

PICMG: Where can interested parties go to find more information on CXL?

JENS: The CXL Consortium website serves as the primary repository of knowledge. This platform not only provides access to the official CXL specifications and technical documents, but also offers insights into the latest developments, industry adoption stories, and educational resources.

More Information:
• Compute Express Link: https://computeexpresslink.org
•*PICMG COM-HPC Overview: https://www.picmg.org/openstandards/com-hpc
•*PICMG Platform Management Interface Specification: https://www.picmg.org/product/com-hpc-platform-management-interface-specification

January 18, 2024

MicroTCA.0 Revision 3 Delivers 4x Performance Improvement with 100 Gigabit Ethernet, PCIe Gen 5 in up to 12 Slots

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Latest MicroTCA revision adds high-bandwidth interfaces and increased TDP to prepare the specification for demanding next-generation edge and server workloads

WAKEFIELD, MA. PICMG, a leading consortium for the development of open embedded computing specifications, has ratified Revision 3.0 of the MicroTCA.0 (µTCA.0) specification. This new release addresses urgent bandwidth requirements by defining 100 GbE and PCIe Gen 5 fabrics that improve system performance by 4x while also expanding platform thermal design power (TDP), enabling the use of higher performance processors. Users can now select from a range of specification-compliant building blocks and solutions that allow for more power per slot for higher transfer rates within µTCA chassis and to external systems and server clusters. It also lays the foundation for building next-generation MicroTCA proofs of concept.

Revision 3 of MTCA.0 addresses the current and future demands of applications such as machine vision, AI, defense, research, instrumentation, wireless communication, and emerging applications like quantum computing. “Revision 3 of MTCA.0 addresses urgent requirements and thus enables companies to now provide specification-compliant solutions rather than proprietary or custom approaches,” says Heiko Korte of NAT Europe and lead of PICMG’s MicroTCA Technical Working Group. “The fact that so many MicroTCA ecosystem suppliers have joined the working group shows the importance of the changes and also underlines the strong interest to make these part of an open specification.

“The broad spectrum of participants also ensured that every single agenda item got reviewed from different angles and properly discussed,” he adds.

MicroTCA.0 Revision 3.0-compliant solutions will be available shortly, including chassis, MicroTCA Carrier Hub (MCH), Advanced Mezzanine Card (AMC), Rear Transition Module (RTM), and power modules (PM) products from VadaTech, NAT, AIES Sp z o.o., nVent SCHROFF, and others. The commitment of existing vendors to continuing the development of µTCA products is joined by increased interest from players in emerging fields like quantum computing, projecting a healthy lifecycle for the open computing specification for years to come.

“VadaTech is proud to have been part of the development and ratification of revision 3 of the uTCA specification,” says Alex Malcom, Managing Director of VadaTech Ltd. “Its release secures the continued adoption of the standard by commercial, scientific and defense organizations around the world.”

The MicroTCA.0 Revision 3.0 specification can be accessed at www.picmg.org/product/micro-telecommunications-computing-architecture-base-specification. For more information on the MicroTCA family, visit https://www.picmg.org/openstandards/microtca.

About PICMG

Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are over 130 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.

 

Key standards families developed by PICMG include COM-HPC, COM Express, CompactPCI, AdvancedTCA, MicroTCA, AdvancedMC, CompactPCI Serial, SHB Express, MicroSAM, and HPM (Hardware Platform Management). https://www.picmg.org.

November 29, 2023

PICMG 2023 in Review: Specs, Specs and More Specs

COM ExpressCOM-HPCJess IsquithMicroTCAMicroTCAOpen Standards

By Jessica Isquith, President, PICMG

The end of every calendar year provides an opportunity to reflect on our achievements and shortcomings. But as 2023 draws to a close, I’m nothing short of astonished with what our membership has accomplished.

Seven specifications have reached significant milestones this year alone:

  1. COM-HPC 1.2. The latest and most advanced COM on the market was upgraded (to a smaller size) with the release of the COM-HPC 1.2 spec revision. Dubbed COM-HPC “Mini”, the 95 mm x 60 mm platform loses a connector compared to its fellow COM-HPC form factors, but still delivers 400 pins for carrying high-speed signals from the processor module to carrier boards.
  2. COM Express 3.1. The established leader in the computer-on-module (COM) market upgraded interfaces to provide increased speed and bandwidth over the previous generation. This will keep the specification compatible with leading-edge processor technologies.
  3. MicroTCA R3.0. MicroTCA continues its 15-year evolution, as Revision 3.0 of the specification add 100 GbE and PCIe Gen 5 interfaces to cement the open platform in high-energy physics and scientific research, communications, and medical applications for years to come. MicroTCA is also a favorite of Quantum Computing startups, many of whom have already adopted the standard in their R&D efforts.
  4. ModBlox7. The first open standard Box PC, ModBlox7, is in its final review phase and expected to be ratified by Q1 2024. It’s modularity, flexibility, and scalability is poised to address the demands of today’s industrial and transportation use cases.
  5. IoT Specs. PICMG’s IoT specification efforts continue to expand as work with Redfish APIs was formally adopted by the DMTF. With continued effort and adoption, the IoT.x family of specifications will enable sensor-to-controller-and-beyond data transparency that will drive the need for and application of compute intelligence at the edge.
  6. CompactPCI Serial Extension. CompactPCI, one of the original PICMG specifications, lives on in the form of CompactPCI Serial. A specification extension adds PCI Express Gen 4, 100 GbE, and support for other modern serial signals. The upgraded performance will allow CompactPCI Serial Extensions to keep targeting industry and transportation platforms where it has been successful for decades.
  7. InterEdge. InterEdge defines a set of specifications for process and automation control for the rugged far edge. This effort is a collaboration between PICMG and OPAF of the OpenGroup and backed by leaders in the energy and industrial markets. It is scheduled for release in early Q1.

All these accomplishments set PICMG up for an exciting 2024, which also happens to be the consortiums 30th anniversary of developing open embedded computing standards. With multiple new specifications primed to enter the industry, we’re looking forward to keeping up the momentum we’ve built over the last calendar year thanks to the hard work and determination of our member companies.

In addition to thanking existing members for their consistent contributions, we invite non-member companies to become part of the specification development process by joining and participating in PICMG. Through collaboration, significant problems are being solved that are reshaping multiple industries with open, interoperable solutions that enable thousands of embedded solutions to reach the market in an efficient and timely fashion.